By Foivos S. Zakkak, Dimitrios Chasapis (auth.), Chenggang Wu, Albert Cohen (eds.)
This ebook constitutes the refereed post-proceedings of the tenth overseas Symposium on complicated Parallel Processing applied sciences, APPT 2013, held in Stockholm, Sweden, in August 2013. The 30 revised complete papers awarded have been rigorously reviewed and chosen from sixty two submissions. The papers disguise a variety of subject matters shooting the various cutting-edge and perform in parallel structure, parallel software program, concurrent and allotted structures, and cloud computing, with a spotlight on computing structures for large information applications.
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Extra info for Advanced Parallel Processing Technologies: 10th International Symposium, APPT 2013, Stockholm, Sweden, August 27-28, 2013, Revised Selected Papers
This design allows for an efficient dependence analysis while limiting the complexity of accessing and updating the same data structures for every block. Using solely memory address ranges to describe the memory footprint of a task restricts tasks to finite footprints. Moreover, it prohibits tasks from allocating memory, as the new range is yet unknown at task-invocation time, and thus cannot be part of the footprint. To address these issues and allow tasks to operate on dynamic data structures, we also use a region-based allocator .
The dependence analysis on blocks is quite similar to dependence tracking on whole objects. There can be, however, extra overhead, as a task argument may consist of multiple blocks, and dependencies must be tracked on each such block. BDDT allows multiple blocks to share the same metadata information. Then, critical dependence tracking operations operate on one metadata element instead of multiple, reducing the overhead of dependence tracking. We use this mechanism in particular to track dependencies on strided arguments—usually multidimensional array tiles: while dependencies are tracked on each block individually, the runtime system registers a single metadata element for all the blocks in the tile.
Each 8-core processor has its own NUMA partition, yielding a total of 4 NUMA partitions with 8 GB of DRAM per partition. To uniformly distribute application data on all NUMA nodes, we initialize input data in parallel. Each core allocates and touches a part of the input array(s) used in each benchmark, so that all NUMA partitions perform approximately the same number of off-chip memory accesses during execution. 1 Benchmarks We use a set of task-based benchmarks to evaluate BDDT. All benchmarks use rowmajor (C-language) array layout.